Researchers at MIT have unveiled a groundbreaking nanoscale transistor that promises to revolutionize electronics by offering higher efficiency than traditional silicon-based devices. This innovation addresses the limitations posed by the so-called 'Boltzmann tyranny,' a physical constraint that restricts silicon transistors from operating below a certain voltage, thereby hindering energy efficiency.
The new design incorporates ultrathin semiconductor materials such as gallium antimonide and indium arsenide and employs quantum tunneling—a phenomenon that allows electrons to traverse energy barriers rather than surmount them. This results in a three-dimensional transistor structure consisting of vertical nanowires measuring just a few nanometers in width, enabling operation at significantly lower voltages while maintaining performance comparable to state-of-the-art silicon transistors.
Yanjie Shao, an MIT postdoctoral researcher and lead author of the study, stated, "This is a technology with the potential to replace silicon, allowing for the same functionalities with improved energy efficiency." The new tunneling transistors exhibit a sharp transition between 'off' and 'on' states at lower voltages, a feat that traditional silicon transistors struggle to achieve efficiently.
The engineering of these transistors utilizes quantum confinement to control electron behavior within a confined space, enhancing their tunneling capabilities. MIT's advanced facility, MIT.nano, facilitated the creation of precise 3D geometries necessary for this effect, resulting in the smallest reported 3D transistors to date, with diameters as small as 6 nanometers.
According to Jesús del Alamo, senior author and Donner Professor of Engineering, "With conventional physics, there is only so far you can go. Yanjie's work demonstrates that we can surpass these limits by employing different physics. While there are numerous challenges ahead for commercial viability, this breakthrough holds significant promise."
The research team, which includes professors Ju Li, Marco Pala, and David Esseni, is now focused on refining fabrication techniques to achieve greater consistency across chips. They are investigating alternative vertical designs to mitigate the impact of small inconsistencies at the nanometer scale on device performance. This study, published in Nature Electronics, received partial funding from Intel Corporation, highlighting the industry's keen interest in advancing beyond traditional silicon technology.